Yield Optimisation of Power-On Reset Cells and Functional Verification

Simulation based yield optimisation is becoming an important solution for increasing robustness of analog IP blocks. This paper describes the yield optimisation of a power-on reset cell as part of an analog IP library. Yield analysis of the initial design is performed and sensitivities with respect to process parameters are determined by Monte Carlo simulation. The input parameters used for the Monte Carlo simulation describe global and local variations of the semiconductor devices. The results of the yield analysis are used to determine a shift of the PMOS threshold implant dose enabling a yield enhancement of the initial design. A re-design using simulation-based design centering is performed resulting in a significant yield increase in consideration of the operating conditions. The optimisation is based on an algorithm maximizing the worst-case-distance. The simulation results on improved production yield are verified by electrical test at wafer level for varying process conditions.